Static random access memories (SRAMs) generally include a number of SRAM cells arranged into an array. The typical SRAM cell includes a flip-flop (FF) having an output connected to a bit line through a switch. The switch is controlled by a word line. In this arrangement, data can be written into, or read from the FF by turning on the switch associated with the memory cell. Following a read or write operation to an SRAM cell, the switch within the SRAM cell is turned off, to thereby separate the output of the FF from the bit line. Once separated from a memory cell FF, a bit line can still maintain a logic potential. Accordingly, if another memory cell is immediately accessed, the residual logic potential on the bit line can change the logic within the FF of the newly accessed cell. To avoid such adverse consequences, bit lines can be "pre-charged" between read or write operations.
In the case where a SRAM includes bit lines pairs associated with each SRAM cell, a pre-charge operation can involve pre-charging the bit line pair by way of a pre-charge and equalization circuit. Such circuits can pre-charge both bit lines of the bit line pair to a "Vcc" voltage level, where Vcc is a supply voltage that is applied to the FF of the SRAM memory cells.
For a SRAM that utilizes bit line pairs in a read operation, once an SRAM cell is accessed, the potential of one of the bit lines of the bit line pairs will drop in potential. The potential drop is relatively small. However, in the case of a write operation, in the event the FF logic value must be inverted, the logic of a bit line may have to drop to a logic low level (GND). As a result, the function of pre-charging a bit line from such a logic low level (GND) to the high (Vcc) pre-charge level, can add a relatively large amount of time to a write operation. Looked at in another manner, following a write operation, a certain amount of time must pass before a subsequent read or write operation can be performed.
According to the present specification, the general time period that is required to pass following a write operation, before a subsequent read or write operation can be performed, is referred to as a "write recovery" time period. Thus, once a write operation has been performed, if a device switches to a subsequent read or write operation before the write recovery period, a mis-writing or misreading operation may occur. Furthermore, for consecutive write operations, the write recovery time can contribute to overall longer write periods, preventing higher speed write operations.
To improve write speeds, "write recovery" circuits are often employed. A number of conventional write recovery circuits will now be described.
Referring now to FIG. 9, a conventional semiconductor memory device is set forth in a block diagram, and designated by the general reference character 900. The semiconductor memory device 900 appears in the Unexamined Japanese Patent Application No. 6-20475, filed on Jul. 3, 1992 and laid open to the public on Jan. 28, 1994. The semiconductor memory device 900 is shown to include a memory cell 902, a bit line load 904, a write bit line load 906, a bit line pair shorting circuit 908, a write line pair shorting circuit 910, a column select line 912, a column gate 914, a write data line load 916, a writing circuit 918, an input buffer 920, a write control circuit 922, a data change detect circuit 924, a control pulse generating circuit 926, a word line drive circuit 928, and a bit line load drive circuit 930. Also set forth in FIG. 9 are bit lines BL and /BL, a word line WL, and write lines WB.
FIG. 10 is a timing diagram illustrating the operation of the various device parts of the semiconductor memory device of FIG. 9.
The conventional semiconductor memory device 900 of FIG. 9 is designed to allow a write operation to memory cell 902 to take place in response to changes in input data values or the application of a write enable signal. In particular, in response to an active write enable signal (/WE transitions low), or in response to a change in data values at the input buffer 920, the data change detect circuit 924 will activate a data change detect pulse (shown as DTD in FIG. 10). The DTD pulse is applied to the control pulse generating circuit 926, which generates a control signal pulse (shown as WEIN in FIG. 10). The WEIN signal pulse is received by the word line drive circuit 928, which activates the word line WL. The activation of word line WL results in the selection of memory cell 902. Data can then be written into the memory cell 902.
Once the writing of data into memory cell 902 has been completed, the write control circuit 922 applies control signals to the bit line load driving circuit 930, which in turn, deactivates the bit line load 904 and the writing circuit 918.
The control pulse generating circuit 926 and word line drive circuit 928 are constructed in such a manner that once the write operation has been completed, the word line WL falls, preventing data from being further written into the memory cell 902. Once in this state, the control pulse generating circuit 926 provides another control pulse to the bit line load driving circuit 930. In response to the signal provided by the control pulse generating circuit 926, the bit line load driving circuit 930 activates the write bit line load 906. Consequently, transistors T900 and T902 turn on, pre-charging the bit lines BL and /BL to the level Vcc.
Also following the completion of a write operation, the control pulse generating circuit 926 outputs a third control signal that is applied to write data line load 916 and a fourth control signal that is applied to the bit line shorting circuit 908. In response to the third control signal, the write data line load 916 is activated, turning on transistors T904 and T906, and thereby raising the voltage of the write lines WB. In response to the fourth control signal, the bit line shorting circuit 908 is activated, turning on transistor T908. Consequently, the bit lines (BL and /BL) are shorted together, and the write lines (WB), due to the operation of the column gate 914, are also shorted together.
In this way a pre-charging operation is performed that is capable of rapidly raising a bit line (BL or /BL) from a low logic level, and thereby achieving a desirable write recovery time.
A drawback to the pre-charge approach set forth in FIG. 9 is the delay that can be introduced by the transistors of the load circuits (904, 906 and 916). As set forth in FIG. 9, the bit lines (BL and /BL) and write lines (WB and /WB) are pre-charged by activating n-channel transistors. In particular, bit lines (BL and /BL) are pre-charged by turning on transistors T900 and T902, and write lines (WB and /WB) are pre-charged by turning on transistors T904 and T906. In the case where a bit line (or a write line) is pre-charged from a logic low level (V=0 V) to a logic high level (Vcc), while the bit line (or write line) has a relatively low voltage, the associated n-channel transistor will remain activated, drawing current and pre-charging the bit line (or write line). However, as the voltage of the bit line (or write line) rises to the Vcc-Vtn level (where Vtn is the threshold voltage of the n-channel transistor), the n-channel transistor will turn off, preventing current from being drawn through the n-channel transistor. This can delay the overall pre-charge operation.
Referring now to FIG. 11, a block diagram of another conventional semiconductor memory device is set forth. The semiconductor memory device illustrated in FIG. 11 appears in the Unexamined Japanese Patent Application No. 4-76894, filed on Jul. 7, 1990 and laid open to the public on Mar. 11, 1992. The semiconductor memory device is designated by the general reference character 1100, and is shown to include a memory cell 1102, pre-charging circuits (1104 and 1106), a column selecting circuit 1108, and a write recovery pulse generating circuit 1110. In addition, FIG. 11 illustrates a bit line pair (BL and /BL), a word line WL, write bus lines (WB and /WB), read bus lines (RB and /RB), a sense amplifier SA, and a write amplifier WA.
FIG. 12 is a timing diagram illustrating the operation of the various device parts of the semiconductor memory device of FIG. 11.
The write amplifier circuit WA provides output signals to the write bus (WB and /WB) according to the logical product of a chip select signal (shown as /CS in FIG. 12), a write enable signal (shown as /WE in FIG. 12), and a data input signal (shown as Din in FIG. 12). A WRPG circuit 1110 is provided for each write bus (WB and /WB). The WRPG circuit 1110 is shown to include an input NOR gate G1100 having inputs coupled to the write bus (WB and /WB), and a delay circuit that includes buffers (B1100 and B1102) and inverter I1100. In addition, the WRPG circuit 1110 includes an output NAND gate G1102. In this arrangement, the write amplifier WA provides output signals to the WRPG circuit 1110 in synchronism with a write operation to memory cell 1102.
Prior to a write operation, the write bus lines (WB and /WB) are both low. During a write operation, according to changes in an applied address (shown as waveform A1 in FIG. 12) the word line WL is driven to a logic high level. In addition, in order to drive one of the bit lines (BL or /BL) high, one of the outputs from the write amplifier WA will be driven high. Consequently, one of the write bus lines (WB and /WB), which were both previously low, will be driven high. The low-to-high transition in one of the bus lines (WB and /WB) results in one of the inputs to gate G1100 going from low to high. Consequently, the output of gate G1100 (shown as WP in FIG. 12) will transition from high to low.
The high-to-low transition in the output of gate G1100 is applied as one input to gate G1102. In addition, the high-to-low transition is applied to the other input by way of delay circuit (B1100, I11100 . . . B1102). In the particular arrangement of FIG. 11, delay circuit inverts and delays the output of gate G1100. As a result, the high-to-low transition at the output of gate G1100 will generate a low-going pulse at the output of gate G1102. The output of gate G1102 is shown as waveform WRP in FIG. 12, and is applied to the pre-charging circuits 1104 and 1106. In this arrangement, on the terminating (high-going) edge of the WP signal, which indicates the completion of a write operation, a low-going WRP pulse is generated. The low-going WRP pulse turns on transistors T1100 to T1104 within pre-charge circuit 1104, and turns on transistors T1106 to T1110 within pre-charge circuit 1106.
For conventional semiconductor memory devices such as that illustrated by FIG. 11, the arrangement of multiple memory blocks can result in a single write recovery pulse (WRP) arriving to different memory blocks at different times. To provide a more uniform response, a write recovery pulse generating circuit (such as 1110) can be supplied to each write bus (WB and /WB). In addition, pre-charge circuits (such as 1104 and 1106) are supplied for the bit lines (BL and /BL) and for the read bus (RB and /RB).
A drawback to the pre-charge approach set forth in FIG. 11 is the area required for implementing such a scheme. In particular, for each bit line pair (BL and /BL) a pre-charge circuit 1104, must be provided. In addition, for each read bus (RB and /RB), another pre-charge circuit 1106 must also be provided. Furthermore, in order to limit differences in the timing of write pulses (such as WRP), a write recovery pulse generating circuit 1110 is required for each write bus (WB and /WB). Each such circuit (1104, 1106 and 1110) requires a certain amount of area on a semiconductor memory device. Consequently, as memory devices are scaled up in size, the number of bit lines, read bus lines, and write bus lines will increase. This requires a corresponding number pre-charge circuits (1104 and 1106) and write recovery pulse generating circuits 1110, which requires additional area. Additional device area can lead to increased manufacturing costs.
As data processing devices, such as central processing units (CPUs), continue to have higher operating speeds, memory devices are required to operate at a correspondingly faster speed. Accordingly, write recovery time periods are of increasing importance.
In light of the need for faster semiconductor memory devices, and the undesirability of increasing circuit area, it would be desirable to arrive at some way of decreasing the write recovery period of a semiconductor memory device. At the same time, such an approach should not result in significant increases in the overall area of the semiconductor memory device.